ITSW 2009 - Call for Papers

CALL FOR PAPERS

Scope -- Submissions -- Key Dates -- Additional Information -- Committees

Scope

Since the inception of ITSW in Santa Barbara in 1994 chip geometries have shrunk from 500 to 45 nanometers with smaller geometries on the near horizon. Digital circuit speeds have moved from the 100-200 MHz range to 2-3 GHz and higher. This amazing shrinkage and speedup has been spurred by innovative algorithms, tools, and methodologies in all aspects of digital chip design and manufacturing. The widespread use of Test Synthesis coupled with powerful pre-silicon verification approaches is one factor that has enabled test to keep up with the increasing chip complexity.

This year ITSW moves to a new location at the University of Texas, Austin. This year’s workshop will look at all aspects of test synthesis such as system bringup, system debug tools and architectures, re-use of pre-silicon DFT structures for post-silicon testing, hand-off of test IP, defect modeling, system test coverage metrics, SiP testing, system-level diagnostic methods, emerging standards for embedded testing, No Trouble Found methods, dealing with variations and imperfections inherent in the manufacturing process etc. As always ITSW will consider papers in any area of Test Synthesis including, but not limited to:

Register Transfer Level DFT
High-Level/Behavioral Test Synthesis
System-on-a-Chip (SOC) DFT
Memory and Logic BIST
Test Synthesis for Debug and Diagnosis
DFT for Mixed-Signal Circuits
Test Resource Partitioning
Functional Verification
DFT for Emerging Technologies

Power and Noise-Aware Test
DFT for At-Speed Test
High-speed I/O test
Reducing the Cost of Test
Design for Manufacturing and Yield
Board and System Test
SER / Reliability
Test Synthesis for Reconfigurable Logic

Submissions

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To present recent research results at the workshop, please submit an extended abstract, one to three pages long, in PDF format, to the Program Chair by January 7, 2009. Acceptance notifications will be sent out on February 9, 2009. Please include the names, affiliations, and full contact information of all authors. Also, indicate which author will be the speaker if the abstract is accepted for presentation. To support open discussion, no formal proceedings of the workshop will be published. As in previous years, ITSW will present a BEST Student Paper Award to encourage student participation in the workshop.

Key Dates

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Submission deadline: January 7, 2009
Notification of acceptance: February 9, 2009

Additional Information

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For general information, contact:
Jennifer Dworak, General Chair
Division of Engineering
Brown University, Providence, RI, USA
Phone: 401.863.1531, Fax: 401.863.9039
Email: GeneralChair@tttc-itsw.org

Submit extended abstracts via email to:
Abhijit Jas, Program Chair
Design and Technology Solutions
Intel Corporation, Austin, TX 78746
Phone: 512.732.3978, FAX: 512.732.3912
Email: ProgramChair@tttc-itsw.org

Committees

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General Chair
J. Dworak – Brown U.

Past Chair
N. Mukherjee – Mentor Graphics

Vice Chair
S. Chakravarty - LSI

Program Chair
A. Jas – Intel

Panels Chair
S. Khatri – Texas A&M U.

Embedded Tutorials Chair
V. Chickermane - Cadence

Publicity Chair
B. Foutz – Cadence

Finance Chair
S. Patil – Intel

Local Arrangements Chair
N. Touba – U. Texas, Austin

European Liaison
M. Zwolinski – U. Southampton

Asian Liaison
C. W. Wu – Nat. Tsing Hua U.

Program Committee
M. Abadir – FreeScale
R. Aitken – ARM
K. Balakrishnan – AMD
C. Barnhart – SiliconAid
K. Chakrabarty – Duke U.
K.-T.Cheng – UC Santa Barbara
A. Crouch – Asset-Intertech
R. Datta – TI
S. Davidson – Sun Micro.
C. Dixit – LSI
A. Guettaf – Broadcom
M. Hsiao – Virginia Tech.
K. Iwasaki – Tokyo Metro. U.
R. Kapur – Synopsys
M. Laisne – QualComm
K.-J. Lee – Nat. Cheng-Kung U.
A. Majumdar – Sun Micro.
S. Mitra - Stanford
K. Mohanram - Rice U.
M. Nourani –U. Texas, Dallas
A. Orailoglu – UC San Diego
B. Pouya – Freescale
J. Qian – Cisco
J. Rajski – Mentor Graphics
S. M. Reddy – U. Iowa
M. Tahoori – Northeastern U.
S. Tragoudas – S. Illinois U.
H. Walker – Texas A&M U.
Li-C. Wang – UC Santa Barbara

For more information, visit us on the web at: http://www.tttc-itsw.org

TheInternational Test Synthesis Workshop (ITSW 2009) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).

TTTC's Electronic Broadcasting Service
	16th International Test Synthesis Workshop (ITSW 2009) March 23-25, 2009 University of Texas at Austin Austin, Texas, USA http://www.tttc-itsw.org